| 著作 |
| 名稱 | 高啟洲譯，“應用數值方法－使用MATLAB，”滄海圖書資訊公司(ISBN: 978-986-157-660-2)。原著：Steven. C. Chapra, 2008, “Applied Numerical Methods with MATLAB for Engineers and Scientists,” 2nd Ed. Mc Graw Hill. |
| 年度 | 2010 |
| 類別 | 學術專書 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs |
| 年度 | 2001 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Improved Three-Step-Search Algorithm for Block Matching Motion Estimation and Its ASIC Design |
| 年度 | 2002 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Technology Mapping Algorithm for Heterogeneous FPGAs |
| 年度 | 2002 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design of Echo Cancellation and Noise Elimination for Speech Enhancement |
| 年度 | 2003 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Efficient Algorithm for Finding the Minimal Area FPGA Technology Mapping |
| 年度 | 2005 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design of Interactive E-Learning System |
| 年度 | 2005 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Spatiotemporal Unsupervised Segmentation Algorithm for Video on-Chip System |
| 年度 | 2006 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design of Field Programmable Gate Arrays with Hierarchical Interconnection Structures |
| 年度 | 2006 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Automated Layout Generator for Analog CMOS Circuits,” International Journal of Electronics |
| 年度 | 2007 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A High Flexibility Design for Clock Distribution Network in System on Chip |
| 年度 | 2007 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Computer-Aided Crosstalk Minimization Design for System-on-Chip |
| 年度 | 2008 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Performance-Driven Rotational Invariant Image Retrieval System |
| 年度 | 2010 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Optimisation Communication Cost Algorithm for Dynamically Reconfigurable FPGAs |
| 年度 | 2010 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Performance-Driven Methods for Fine Granularity Scalable Video Coding |
| 年度 | 2010 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Efficient Rotation and Reflection Invariance Region-Based Image Retrieval Framework
|
| 年度 | 2010 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Heuristic Algorithms for Constructing Interference-free and Delay-Constrained Multicast Trees for Wireless Mesh Networks |
| 年度 | 2011 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Low Energy Cluster Head Prediction for Wireless Sensor Network |
| 年度 | 2011 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | High Performance Rotation CORDIC Algorithm Based on Look-Ahead Techniques |
| 年度 | 2011 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | BDD Synthesis for Mixed COMS/PTL Logic |
| 年度 | 2011 |
| 類別 | 期刊論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design and Implementation of Car Navigation and Cockpit Infotainment Embedded System on Open Service Gateway initiative |
| 年度 | 2012 |
| 類別 | 期刊論文 |
| 摘要 | When wireless broadband technology is advanced increasingly in communication environment, the intelligent traffic information system research has been paid much attention. The purpose of this paper is to provide real-time vehicle location information and network communication services by building an open platform for embedded automotive information services and integrating the embedded technology, satellite positioning, and 3G mobile communications with wireless local area network. In this paper, the vehicle information system platform will be constructed on the Open Service Gateway initiative (OSGi). Using the OSGi platform, the vehicle information system can be intelligent vehicle systems. The main feature of our system not only provides general common traffic navigation system but also gives the forward-looking cockpit of multimedia services. |
| 關鍵字 | OSGi, Multimedia, Car System, Global Positioning System, and Embedded System |
| 名稱 | Interface Circuit Synthesis of System-on-Chip |
| 年度 | 2012 |
| 類別 | 期刊論文 |
| 摘要 | Most of the Intellectual Properties (IPs) of System-on-Chip (SoC) are provided by different vendors, and thus they may have various characteristics, making the interface circuit synthesis of SoC a time-consuming and error-prone process. The main contribution of this paper is to present an interface synthesis algorithm for power minimization in interface circuit design of SoC. Moreover, we also study the power and area trade-off in interface circuit synthesis of such systems. By starting from the power-minimal solution, we perform a sequence of power relaxation operations and area-minimizing procedures to produce a set of solutions for a given SoC interface circuit design with power and area trade-off considerations. The experimental results demonstrate the effectiveness of our algorithms. |
| 關鍵字 | |
| 名稱 | Fast Intra Prediction Mode Decision for H.264/AVC Video Coding |
| 年度 | 2013 |
| 類別 | 期刊論文 |
| 摘要 | Intra coding is used for reducing the spatial redundancy in video coding. H.264 supports several macroblocks of predictions for intra coding such as luma block four 16616
modes, nine 464 modes and chroma block four modes, which significantly improve intra coding efficiency, but increase the encoding complexity. In order to select the best mode, we need to calculate the cost of the various modes. In this paper, a fast intra prediction mode decision for H.264/AVC video coding is proposed. Based on Laplacian, this intra prediction mode decision detects edges and selects the best mode for the block. This mode decision can shorten the time to reduce the encoding time. The experimental results show that the proposed algorithm achieves an encoding time saving of 70% on average. |
| 關鍵字 | H.264, Laplacian, intra mode, video coding, performance |
| 名稱 | Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs |
| 年度 | 2013 |
| 類別 | 期刊論文 |
| 摘要 | The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the eRectives of the algorithm. |
| 關鍵字 | TMFPGA; recon¯gurable computing; communication; architecture; algorithm |
| 名稱 | Energy Efficient System-on-Chip Design for Wireless Body Area Sensor Network |
| 年度 | 2014 |
| 類別 | 期刊論文 |
| 摘要 | This paper presents a novel energy-efficient on-chip design for wireless body area sensor networks (WBASN) focused towards pervasive healthcare applications. The network adopts a master-slave architecture, where the body-worn slave nodes periodically send sensor readings to a central master node. Unlike traditional peer-to-peer wireless sensor networks, the nodes in this WBASN are not deployed in an ad hoc fashion. The network is centrally managed and all communications are single-hop. A cluster algorithm is also presented so that all slave nodes are within the transmission range of the master nodes. It pretends that all slave nodes can share resources and information over the internet to reduce energy consumption. We have simulated for some experiments and implemented the design on system-on-chip platform. Compared to published and industrially used schemes, the power consumption of the proposed design is over 30% and 99% lower in the simulation and platform implementation, respectively. |
| 關鍵字 | |
| 名稱 | Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction |
| 年度 | 2015 |
| 類別 | 期刊論文 |
| 摘要 | Multiple dynamic supply voltage (MDSV) designs
can be used to reduce power consumption. However, power
modes operation with different voltages will cause increasing of the clock skew. The adjustable delay buffers (ADBs) can be used to minimize clock skew under different power modes but it is unlikely to add an unlimited number of ADBs in real world. In the paper, we first assign positions of adjustable delay buffers in a given clock tree to generate zero clock skew. If the number of ADBs is not satisfied with the constraints in the previous solution, a bottom-up method is then used to remove some adjustable delay buffers so that the clock skew is minimized under satisfying all constraints. Finally, the experimental results show that our design is very practical. |
| 關鍵字 | Multiple dynamic supply voltage . Adjustable delay buffers . Clock skew . Determinate . Minimization |
| 名稱 | Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures |
| 年度 | 2015 |
| 類別 | 期刊論文 |
| 摘要 | Dynamic reconfiguration is important for reconfigurable platforms. Parallel reconfigurable computing (PRC) architecture consists of multiple dynamic reconfigurable computing (DRC) units. Thus, for a circuit to be implemented on a parallel reconfiguration system, it needs to be partitioned such that each sub-circuit can be executed to the DRC units in a PRC system. For high performance, this paper proposes a greedy algorithm that maximizes data parallelism for task scheduling of parallel reconfigurable architectures with unlimited resources. The proposed algorithm generates an optimal solution in polynomial time Oen3T, where n is the total number of the
tasks. After obtaining a depth optimal solution, we reduce the resources without decreasing performance by the duplication packing operations whose time complexity is Oen3T. To demonstrate the performance of the proposed algorithm, we not only compare the existing methods with standard benchmarks but also implement on physical systems, like DSP, FIR, and JPEG. The experimental
results show that the proposed algorithms satisfy the requirements of the performance-oriented systems with limited resources. Hence, we have sufficient reason to believe that the runtime must be reasonable for general applications. |
| 關鍵字 | Dynamic reconfiguration, optimization, performance, parallel, and task scheduling |
| 名稱 | Improved Edge-Directed Super Resolution |
| 年度 | 2016 |
| 類別 | 期刊論文 |
| 摘要 | Super-resolution is necessary when the resolution of an image is lower than the screen resolution of a digital display device. Usually, interpolation operation is used in the image super-resolution process. However, the existing image interpolation methods suffer blurring problems in edge regions, so it is hard to produce sharp and clear visual effects. In this paper, we propose an improved edge-directed super-resolution, which keeps the edges sharp and provides good image quality. We first check whether there is an edge or not and then an interpolation method is selected according to the existence and the direction of an edge. Experimental results demonstrate that good image quality can be achieved. |
| 關鍵字 | super-resolution, edge direction, resolution, image interpolation, sharp |
| 名稱 | Shape-Based 3D Model Retrieval System |
| 年度 | 2016 |
| 類別 | 期刊論文 |
| 摘要 | A large number of 3D models are created and available on the Web. Hence, it is necessary to develop efficient methods for retrieving the 3D models in a large database. In the past, 3D model used only the relationship between multi-points but losses the geometric structure of the original model. In this paper, a system, which can save the local geometry information of a model, is presented for robust shape retrieval from 3D models. The main contributions of this system include: 1) developing a high level descriptor of 3D model and 2) presenting algorithms to extract rotational invariant feature representations of a 3D model. The 3D model is first represented by 2D shapes of various angles. Each 2D shape is represented by a discrete set of n points. Next, an efficient algorithm for rotation invariance is proposed. In the algorithm, the shape contexts are clustered and labeled so that the shape contexts in each cluster have the same label. Using the histogram of label frequencies can search quickly and efficiently similar shapes. The experimental results have shown that our system is effective and has better retrieval results than the existing systems. |
| 關鍵字 | retrieval, 3D, rotation-invariance, shape based, and label |
| 名稱 | Design of Low Power Snoop for Multi-Processor System on Chip |
| 年度 | 2016 |
| 類別 | 期刊論文 |
| 摘要 | In multiprocessor system on chip, processors can access expectable shared data by using snoop protocol in different time. However, this design will generate a large number of snoops to consume unnecessary energy. The main objective of the paper is to reduce the number of snoops of the multiprocessor system by using an energy-saving architecture. The proposed method includes two designs: 1) snoop turning point design and 2) snoop buffer design. In the first design, a main key defined as the critical section in which the data accessed synchronously by multiple processors is presented. When the data in critical section are accessed by a processor, the critical section will be locked immediately such that other processors cannot access the data. Because the critical section processors have not common accessing data with the other processors, all snoops are removed after snooping turning point. In the second design, we add buffers to the caches and shared buses to label the number of common data processors. Using the design, only the processors labeled in buffers need to be snooped. The experimental results are shown that the proposed designs can achieve the purpose of energy saving. |
| 關鍵字 | Multi-processor system on chip, Low power, Synchronous communication, Snoop, Coherence |
| 名稱 | Stereoscopic Image Generation with Depth Image Based Rendering |
| 年度 | 2016 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we proposed stereoscopic image generation methods of adjusting the depth value of edge pixels and improved hole filling procedures. For the conventional system, the smooth of depth map can reduce the incidence of image holes, but cause geometric distortions of the image depth. To solve the problems, the depth map is first expanded to refine the accuracy of image depth and the quality of images. Next, we derive a hardware-oriented method for 3D warping. Finally, appropriate blocks are searched to enhance the performance of image by improving hole-filling procedures. The experimental results demonstrate the proposed methods have great performance and practicability. |
| 關鍵字 | Image generation, 3D, DIBR, Pre-processing, Hole-filling |
| 名稱 | Improved Feature Extraction and Classification Methods for Electroencephalographic Signal based Brain-Computer Interfaces |
| 年度 | 2017 |
| 類別 | 期刊論文 |
| 摘要 | It is very important for brain–computer interfaces to classify accurately electroencephalographic signals. In this paper, we proposed an improved feature extraction and classification methods for electroencephalographic signal based brain-computer interfaces. We decompose electroencephalogram signal into bands by using discrete wavelet transform and compute the approximate entropy values. The feature vectors are selected adaptively from statistical wavelet coefficients and approximate entropy values. The support vector machine is used to classify the features. The experimental results demonstrate the proposed system has great performance and reliability. |
| 關鍵字 | electroencephalographic signal, brain-computer interfaces, support vector machine, extraction, classification |
| 名稱 | Stereoscopic Image Generation with Depth Image Based Rendering |
| 年度 | 2017 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we proposed stereoscopic image generation methods of adjusting the
depth value of edge pixels and improved hole filling procedures. For the conventional system,
the smooth of depth map can reduce the incidence of image holes, but cause geometric
distortions of the image depth. To solve the problems, the depth map is first expanded to
refine the accuracy of image depth and the quality of images. Next, we derive a hardwareoriented
method for 3D warping. Finally, appropriate blocks are searched to enhance the
performance of image by improving hole-filling procedures. The experimental results demonstrate
the proposed methods have great performance and practicability. |
| 關鍵字 | Image generation . 3D . DIBR . Pre-processing . Hole-filling |
| 名稱 | Design of Low Power Snoop for Multi-Processor System on Chip |
| 年度 | 2017 |
| 類別 | 期刊論文 |
| 摘要 | In multiprocessor system on chip, processors can
access expectable shared data by using snoop protocol in different
time. However, this design will generate a large number
of snoops to consume unnecessary energy. The main objective
of the paper is to reduce the number of snoops of the multiprocessor
system by using an energy-saving architecture. The
proposed method includes two designs: 1) snoop turning point
design and 2) snoop buffer design. In the first design, a main
key defined as the critical section in which the data accessed
synchronously by multiple processors is presented. When the
data in critical section are accessed by a processor, the critical
section will be locked immediately such that other processors
cannot access the data. Because the critical section processors
have not common accessing data with the other processors, all
snoops are removed after snooping turning point. In the second
design, we add buffers to the caches and shared buses to
label the number of common data processors. Using the design,
only the processors labeled in buffers need to be
snooped. The experimental results are shown that the proposed
designs can achieve the purpose of energy saving. |
| 關鍵字 | Multi-processor systemon chip . Low power . Synchronous communication . Snoop . Coherence |
| 名稱 | Mapping Virtual Tasks onto Physical Devices for Cloud Computing |
| 年度 | 2018 |
| 類別 | 期刊論文 |
| 摘要 | Cloud computing is a commercial infrastructure that eliminates the need for maintaining expensive computing facilities. In this paper, a virtual network is a set of nodes with edges that denote the communication bandwidth requirement between them, while a physical network denotes a set of physical nodes with edges that represent the available physical resources. Our goal is to map the virtual nodes of the physical nodes and find a physical resource allocation to meet the logical network demands, subject to physical network constraints. An efficient approach is proposed to achieve a feasible virtual to physical mapping. Experiments were conducted to demonstrate the efficiency of the proposed algorithms. |
| 關鍵字 | assignment, cloud computing, flow, mapping, node |
| 名稱 | Design and Implementation of Stereoscopic Image Generation |
| 年度 | 2018 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we proposed the design and implementation of a new stereoscopic image
generation system. In the conventional system, the smoothness of depth map can reduce the
incidence of image holes, but cause geometric distortions of the image depth. To solve the
problems, the depth map is ¯rst re¯ned to increase the accuracy of image depth and the quality
of images. Next, we derive a hardware-oriented method for 3D warping and improve hole-¯lling
procedures to enhance the performance of image. Finally, the circuit design is presented
according to the proposed stereoscopic image generation system to achieve real-time applications.
The experimental results demonstrate that the proposed system can improve by 10–27%
when compared to existing methods. |
| 關鍵字 | Image generation; 3D; DIBR; circuit design; hole-filling |
| 名稱 | Design and Implementation of Mobile Smart Home System |
| 年度 | 2019 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we propose a mobile smart home system includes a high-sensitivity signal
interface transmitting end, a low-cost signal interface receiving end, and a mobile APP interface
device connected the two ends for the user to control the smart home. After receiving the signal
of the signal transmitting end, the signal can be sent to the receiving end through the APP
interface device according to the user request to achieve the purpose of realizing the smart
home system. The present invention has the advantages of low cost, high sensitivity and
convenient operation. |
| 關鍵字 | intelligent family, platform, phone, wireless communications, development board |
| 名稱 | C Language Learning Platform for Primary Students |
| 年度 | 2019 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we propose a C-language learning platform for primary students includes a Clanguage
learning platform, an interpreter and a translation terminal, and a C language learning
platform. When the user confirms the identity through the login, the user can enter the C
language learning platform. After learning the program learning unit or the question unit, it
will be sent to the translation batch to perform translation, compilation and correction. After
the user understands the error, the system can be used repeatedly until the learning is completed.
The invention translates error messages into easy-to-understand chinese, and there are a large
number of non-choice questions for users to learn, so it is suitable for primary students to learn
C language. |
| 關鍵字 | debug oriented, program design, platform, test library, compiler |
| 名稱 | Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable Architectures |
| 年度 | 2020 |
| 類別 | 期刊論文 |
| 摘要 | In this paper, we propose a resource/performance tradeo® algorithm for task scheduling of
parallel recon¯gurable architectures. First, it uses unlimited resources to generate an optimal
scheduling algorithm. Then, a relaxation algorithm is applied to satisfy the number of resources
under increasing minimum performance. To demonstrate the performance of the proposed
algorithm, we not only compare the existing methods with standard benchmarks but also
implement on physical systems. The experimental results show that the proposed algorithms
satisfy the requirements of the systems with limited resources. |
| 關鍵字 | Parallel recon¯gurable computing; resource; performance; tradeoff; scheduling |
| 名稱 | Design of Embedded Sensor System with Parallel Reconfigurable Computing Platform |
| 年度 | 2020 |
| 類別 | 期刊論文 |
| 摘要 | Embedded devices and sensor networks are becoming popular and cheap, enabling the
design of an alternative pathology detection system to monitor structures based on these
technologies. On the other hand, configurable computing machines are evolving rapidly. The
parallel reconfigurable computing can connect to high-speed microcontroller and peripheral
equipment of the embedded system. Based on those reasons, we use parallel reconfigurable
computing as the signal processing core to integrate the different transmission interface and
generate an embedded sensor system. Compared with other work, the embedded system design
satisfies the ease of use, fault tolerance, scalability, low consumption, and flexibility
requirements. The experimental results demonstrate the proposed system has great performance
and practicability. |
| 關鍵字 | configurable computing, embedded system, sensor, parallel, PRC |
| 名稱 | Performance-Driven Parallel Reconfigurable Computing Architecture for Multi-Standard Video Decoding |
| 年度 | 2020 |
| 類別 | 期刊論文 |
| 摘要 | Video processing applications often need high computing capacity but have performance
and power constraints, especially in portable devices. General purpose processors can no
longer meet the requirements. This paper presents a parallel reconfigurable computing
architecture consisting of reconfigurable processing units connected by an area-efficient
routing. The hierarchical configuration contexts can cut the implementation overhead and
the energy dissipation spent on fast reconfiguration. The proposed architecture targets
multiple-standard video processing. The design is able to give high performance comparable
to the fixed-function ASIC through deep pipelining and a large amount of computing
parallelism. The experimental results show the proposed architecture has great
performance and practicability. |
| 關鍵字 | Reconfigurable processing . Performance . Power . Parallel .Multiple-standard video processing |
| 名稱 | Improved Fast Intra Mode Decision in H.266/Versatile Video Coding (VVC) Based on Deep Learning |
| 年度 | 2022 |
| 類別 | 期刊論文 |
| 摘要 | H.266/VVC is ultra-high-definition video over 4K, and can be applied in High Dynamic Range Imaging (HDR) and wide color gamut (WCG). However, it has high coding computational complexity based on the coding unit (CU) structure of a quadtree plus binary tree (QTBT). This plan first proposes a fast coding unit spatial features decision method to reduce the coding complexity in H.266/VVC such that the H.266/VVC coding can be speed up. Another important contribution of this plan is to combine video coding with Convolutional Neural Networks (CNNs) in H.266/VVC in-frame coding mode prediction decision. It can be shown that the proposed methods can achieve better encoding performance than the original encoding method (JEM7.0). |
| 關鍵字 | H.266, VVC, CNN, 3-step search |
| 名稱 | Optimizing FPGA-Based Convolution Neural Network Performance |
| 年度 | 2023 |
| 類別 | 期刊論文 |
| 摘要 | In deep learning, convolutional neural networks (CNNs) are a class of artificial neural
networks (ANNs), most commonly applied to analyze visual imagery. They are also
known as Shift-Invariant or Space-Invariant Artificial Neural Networks (SIANNs), based
on the shared-weight architecture of the convolution kernels or filters that slide along
input features and provide translation-equivariant responses known as feature maps.
Recently, various architectures for CNN based on FPGA platform have been proposed
because it has the advantages of high performance and fast development cycle. However,
some key issues including how to optimize the performance of CNN layers with different
structures, high-performance heterogeneous accelerator design, and how to reduce the
neural network framework integration overhead need to be improved. To overcome and
improve these problems, we propose dynamic cycle pipeline tiling, data layout optimization,
and a pipelined software and hardware (SW–HW)-integrated architecture with
flexibility and integration. Some benchmarks have been tested and implemented on the
FPGA board for the proposed architecture. The proposed dynamic tiling and data layout
transformation improved by 2.3 times in the performance. Moreover, with two-level
pipelining, we achieve up to five times speedup and the proposed system is 3.8 times
more energy-efficient than the GPU. |
| 關鍵字 | CNN; FPGA; optimize; performance; architecture |
| 名稱 | Performance-Oriented FFPGA-Based Convolution Neural Network Designs |
| 年度 | 2023 |
| 類別 | 期刊論文 |
| 摘要 | Convolutional neural network (CNN) is the most well-known algorithm that it has been
widely utilized in the applications of the image recognition and classification. Various
Field Programmable Gate Array based (FPGA-based) CNN architectures had been
proposed for the capability of the fast reconfigurability. However, the high-performance
designs are necessary to reduce the computational time. The contributions of the paper
include: 1) using heterogeneous and two-dimensional dispatcher technologies to implement
FPGA-based CNN accelerators at different computational levels of CNN so that the
computational time of CNN can be reduced and 2) proposing a flexible and integrated
pipeline software and hardware (SW/HW) architecture to reduce the integration overheads
of using a CNN framework. The experimental results show that the proposed
architectures have the best performance and minimum FPGA resource requirements. |
| 關鍵字 | CNN . FPGA. Optimize . Performance . Architecture |
| 名稱 | A Field Programmable Gate Array Chip with Hierarchical Interconnection Structure |
| 年度 | 1998 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design and Implementation of an Adaptive FIR Filter based on Delayed Error LMS Algorithm |
| 年度 | 1999 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Quadratic Programming Method for Interconnection Crosstalk Minimization |
| 年度 | 1999 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Routability and Performance Driven Technology Mapping Algorithm for LUT Based FPGA Designs |
| 年度 | 1999 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Technology Mapping Algorithm for Heterogeneous FPGAs |
| 年度 | 2003 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Area-Minimal Algorithm for LUT-Based FPGA Technology Mapping with Duplication-free Restriction |
| 年度 | 2004 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design and Implementation of Interactive E-Learning System |
| 年度 | 2004 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | DTA: Layout Design Tool for CMOS Analog Circuit |
| 年度 | 2004 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Efficient Speech Enhancement Method Using Kalman Filter and Spectral Subtraction |
| 年度 | 2004 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Efficient Video Segmentation Algorithm Based On Accumulative Information Technique |
| 年度 | 2005 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Communication Cost Minimization Algorithm for Dynamically Reconfigurable FPGA |
| 年度 | 2005 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Fast Fine Granularity Scalable Coding for Video Streaming |
| 年度 | 2005 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Optimal Power Algorithm for Interface Design of System-on-Chip |
| 年度 | 2007 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | An Improved Architecture for Optimizing Partitioning Cost of Time-Multiplexed FPGA |
| 年度 | 2007 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Sequential Circuit Partitioning Algorithm for Dynamically Reconfigurable FPGAs |
| 年度 | 2007 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Novel Flash A/D Converter with Ultra Short Latency and High Bubble Error Tolerance |
| 年度 | 2007 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Crosstalk Minimization Method for System-on-Chip |
| 年度 | 2007 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Simple Scheme to Extend the Linearity of the Continuous-Time CMFB Circuit for Fully-Differential Amplifier |
| 年度 | 2008 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | A Novel Digital Pixel Sensor System |
| 年度 | 2009 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Energy Efficient Clustering Communication Protocol for Wireless Sensor Network |
| 年度 | 2010 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Improved Snoop Protocol to Reduce Power in MPSoC |
| 年度 | 2011 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | View Based Rotation Invariant 3D Shape Retrieval,” International Conference on Remote Sensing and Data |
| 年度 | 2011 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Adjustable Delay Buffers Assignment Algorithms for Clock Skew Minimization |
| 年度 | 2012 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Laplacian-Based H.264 Intra-Prediction Mode Decision |
| 年度 | 2012 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Clock Skew Minimization with Adjustable Delay Buffers Restriction |
| 年度 | 2013 |
| 類別 | 會議論文 |
| 摘要 | Multiple dynamic supply voltage (MDSV) designs can be used to reduce power consumption. However, switching of power modes may cause increasing of the clock skew because some modules operate with different voltages. In this paper, the adjustable delay buffers (ADBs) is used to minimize clock skew under different power modes.
We first construct a clock tree to assign positions of adjustable delay buffers. Because adjustable delay buffers can increase additional delays, the clock skew can be optimized. It is unlikely to add an unlimited number of ADBs in real world so the number of ADBs must be limited. If the number of ADBs is not satisfied with the constraints in the previous solution, a bottom-up method is then used to remove some adjustable delay buffers. Finally, the experimental results show that the presented algorithms generate effective improvements.
|
| 關鍵字 | adjustable delay buffers, clock skew, source, assignment algorithm, minimization |
| 名稱 | E-Health Design of EEG Signal Classification for Epilepsy Diagnosis |
| 年度 | 2013 |
| 類別 | 會議論文 |
| 摘要 | Epilepsy, which is caused by abnormal discharges in the brain, is one of the most common neurological disorders.
To diagnose efficiently epilepsy, it is valuable to classify electroencephalogram signal. In this paper, we proposed a new e-health design of Electroencephalogram (EEG) signal classification for epilepsy diagnosis. The design is based on support vector machine to classify electroencephalogram signal. We first decompose electroencephalogram signal into bands by using discrete wavelet transform and compute the approximate entropy values in the bands. Next, by proposed feature selection
method, the feature vectors are selected adaptively from
statistical wavelet coefficients and approximate entropy values. Finally, the support vector machine is used to classify the selected features. The experimental results showed the proposed system has great performance and reliability and the total accuracy of classification can achieve 98%. |
| 關鍵字 | e-health, electroencephalogram signal, |
| 名稱 | Improved Depth-Image-Based Rendering System |
| 年度 | 2016 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Design of Embedded Sensor System Based on Parallel Reconfigurable Computing Platform |
| 年度 | 2016 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Implementation of Stereoscopic Image Generation |
| 年度 | 2016 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |
| 名稱 | Parallel Reconfigurable Computing-Based Architecture for Multi-Standard Video Coding |
| 年度 | 2020 |
| 類別 | 會議論文 |
| 摘要 | |
| 關鍵字 | |